Skip to content

Integration of ETH Zurich DCMAC#159

Open
mariodruiz wants to merge 28 commits into
Xilinx:devfrom
mariodruiz:ethz-dcmac-integration-v2
Open

Integration of ETH Zurich DCMAC#159
mariodruiz wants to merge 28 commits into
Xilinx:devfrom
mariodruiz:ethz-dcmac-integration-v2

Conversation

@mariodruiz

Copy link
Copy Markdown
Collaborator
  • Use ETH Zurich DCMAC as submodule
  • Modify emit logic to match new DCMAC structure
  • Fix traffic producer offset address in the top module to match base layer

Example 06 tested

# TODO: GT quad LOC constraints disabled — cell path changed with versal_dcmac
# hierarchy and the correct path still needs verifying against the netlist.
# set_property LOC GTM_QUAD_X0Y10 [get_cells top_i/service_layer/qsfp_2_n_3/gt_wrapper/gtwiz_versal_0/inst/quad_inst ]
# set_property LOC GTM_QUAD_X1Y7 [get_cells top_i/service_layer/qsfp_0_n_1/gt_wrapper/gtwiz_versal_0/inst/quad_inst ]

Copy link
Copy Markdown
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@hpc-aulmamei do we need this LOC? If yes, I need to figure out the new path

Copy link
Copy Markdown
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

@mariodruiz I don't think this is needed at all.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants